Research And Implementation Of PCI Express Physical Layer

Computer I/O technology is of key importance in the development of high performance computing. The high-speed data rates of PCI Express system architecture make it a very broad prospect for development. PCI Express physical layer occupys a pivotal position in the PCI Express architecture as the bottom layer.The structure and working principle of the PCI Express Physical Layer have been deeply analyzed and researched, then the module has been realized using full custom design method. This thesis mainly contributes to the following aspects:1.A PCI Express physical layer module has been designed and realized which is compatible with the PCI Express standard, the post simulation shows that the module works perfectly at the frequency of 1.5GHz (3.0Gbps).What is more, a dual-edge sampling Serdes is included in this design, which is suitable for the GHz high-speed signal transmission.2.The optimized dynamic circuit is implemented to solve the extreme restriction of the clock duty cycle when using the dual-edge sample structure.3 By using a novel high-speed dynamic register chain with controllable output state, the problem of collision is solved when the high-speed serializer and the Parallel-data-sampler drive the same node at the same time.4.A state-controllable dual-edge sampling lock divider is proposed ,which is used to generate multiple phase clocks.5.Optimized arithmetic of the 8b/10b coding is implemented, it has greatly reduced the complexity of coding ,which has also improved the performance.6.The method for testing the high-speed Serdes is improved by using the LOOPBACK module, which can be helpful to confirm and analysis the fault location.