Design For PCI Express Physical Layer Based On CMOS

This paper briefly overviews the PCI BUS family development course and the advantage of PCI Express BUS, presents the PCI Express 1.1 specifications of PCI-SIG and discusses particularly the circuit design of PCI Express Physical Layer. The designs in this paper include 8B/10B encoder and decoder, Serilazer and Deserilazer, transmitter, and receiver detection and its beacon.The 8B/10B codes mainly investigate the Interco relation of 8B/10B code. To simple the circuit structure and meet the VLSI's requirements, the design adopts a encode/decode method based on logistic design.This paper particularly discusses the operational principle of the Serializer and Deserializer and their difficulties which is possibly to encountered and its' corresponding solutions under condition of high data speed. Meanwhile, this paper describes the core circuits about the Serializer and Deserializer.A novel high-speed serial transmitter, which is constructed by pre-driver and main driver, is demonstrated.A novel receiver comprising three stages circuits, namely, voltage-conversion, data-sampling and data-holding is proposed. The proposed tracking receiver utilizes an over sampling technique to avoid the metastable problem and a digital phase shifting approach to improve the noise immunity, compared to the analog one.The circuit design of the Physical Layer is based on SMIC 0.18um mixed signal model. As the simulation results show, it indicate that under 2.4 Gbps signal transmission rate the all capabilities of the design PL circuit meet the PCI Express 1.1 specifications of PCI-SIG.