Research On Key Techniques For High-speed Dual-mode SerDes Receiver

The large-scale development of cloud computing,Internet and 5G communication technologies have driven us into the era of the Internet of Things,in which all kinds of data has been generated drastically in volume.As a result,the high-speed data processing and communication needs for data center continue to increase.Under these circumstances,high-speed serial link(SerDes)technology has become a key technology to solve these problems of ultra-high-speed data interconnection and to improve data rates and energy efficiency.At the same time,the continuous increase of the data rates makes the design of broadband SerDes circuits more difficult,so that we need four-level amplitude modulation(PAM4)technology to mitigate the bandwidth requirements of circuits as well as to support multi-rate transmission with dual-mode systems.This work aims to design a high speed SerDes receiver compatible with both NRZ and PAM4 modulation,and optimize the equalization circuit to reduce system power consumption and improve hardware-reuse,all of which can make its transmission data rate speed at 32Gb/s.This thesis starts with the research background and application of SerDes system,introduces the composition of SerDes system and summarizes its development and trend.Then key problems to be solved and research goals in this wok are identified.This work also introduces the related basic theory of SerDes communication.And by comparing the advantages and disadvantages of NRZ and PAM4 modulation,the value of research and design a dual-mode transmission SerDes is verified.Then the thesis analyzes the signal integrity theory of the high-speed SerDes system,such as channel insertion loss,inter-symbol interference and crosstalk.Key performance of the entire system is indicated out such as eye diagram,bit error rate,and jitter.Then the principle,circuit design skills and equalization parameter calculation of the linear equalizer and decision feedback equalizer in the receiver are proposed and explained to solve the above problems.Finally,this thesis introduces a reconfigurable high-speed dual-mode receiver supporting both NRZ and PAM4 modulation,and this chip is designed and implemented on the GF 22nm FD-SOI technology.The receiver incorporates an input matching network,an Analog front-end consisting of two-stage CTLE and summer,a 3-Tap dual-mode half-rate decision feedback equalizer(DFE),high-speed PAM4 decoder and deserialization circuit.This work also introduces a digital method for the comparator threshold voltage calibration in PAM4 operating mode.After high-speed circuit layout drawing,the receiver achieves a layout area of750×460 um~2.Post simulation result shows that the receiver achieves a data rate of 16Gb/s which is the maximum data rate in NRZ mode,and it can handle 24dB channel loss,by achieving an energy efficiency of 5p J/bit.In PAM4 mode,the maximum data rate is 32Gb/s under 17.5dB lossy channel,And the energy efficiency is only 2.9p J/bit.