An Efficient Physical Coding Sublayer Design For PCI Express

The Rapid development on computer platform demands the I/O bus toupgrade and the demand on I/O bandwidth drives the conventional parallel bus tobe replaced by the high-speed serial bus gradually. As one of the typicalhigh-speed serial bus applications, PCI Express is the third generation highperformance I/O bus and is of key importance in the development of highperformance computing. Research on the PCI Express bus is important.For PCI Express bus, respectively, researches are done from the systemtopology, the bus architecture and the physical layer function. The basic structureand working principle of the physical layer and the implementation of thephysical coding sublayer are the research priorities.The research on the physical layer function can be divided into two parts:theory and implementation. At the theoretical part, detailed analysis of all thefunctional modules of the physical layer are introduced, including the logicalsub-block layer and the physical sub-block layer. The logical sub-block layerincludes functional modules of data package with dismantling and restructuring,byte striping and un-striping, scrambling and descrambling, encoding anddecoding, symbol lock, frequency compensation, multi-lane phase compensationand link initialization and training while the physical sub-block includesfunctional modules of PLL, clock data recovery, SERDES and differentialtransmitter and receiver. Based on the PIPE interface protocol, the physical layeris divided into media access control layer, physical coding sublayer and physicalmedia attachment layer. At the actual design part, a specific design method ofphysical coding sublayer is introduced, including functional modules of logicoperation of8b/10b encoding and decoding, parallel symbol lock, elastic buffer,power management, receiver state feedback and clock management and design.For the design of physical coding sublayer, many aspects from verificationincluded VCS software simulation and FPGA verification are used to verify itscorrectness and consistency. The software simulation involves module simulation,physical coding sublayer simulation and overall system simulation while theFPGA verification is to verify whether the main data path can properly transmitdata. Based on the PCI Express2.0protocol and the PIPE2.0protocol, the physicalcoding sublayer combined with the physical media attachment layer achieves thephysical layer. The physical layer is finally tapeouted based on the SMIC55nmCMOS process. At the same time, a test system is built and the chip function andperformance tests are with good results.Overall, the physical coding sublayer design has a certain degree ofengineering significance and can provide a reference for future research.