Design Of Physical Coding Subplayer Of Radiation Tolerent 4-lane SerDes

SERializer/DESerializer(Ser Des)is a high-speed serial-to-parallel conversion interface based on time division multiplexing(TDM)and point-to-point communication technology.At the transmitting terminal,the low-speed parallel signals are converted into high-speed serial signals to transfer to the receiving terminal via the channel media(optical cable or copper wire).Finally,the high-speed serial signals are reconverted to the low-speed parallel signals at the receiving terminal.The single-event upset effect and the single-event transient effect often lead to continuous multi-bit errors in the serial data sent by the Ser Des circuit working in space,greatly increasing the bit error rate of the high-speed data transmission system.Therefore,the study on radiation-hardened Ser Des circuits is very meaningful.Based on the radiation-hardened four-channel Ser Des IP,the physical coding sub-layer design is studied,and this paper designs an radiation-hardened four-channel Ser Des high-speed serial-parallel interface,which expands three functions: 8b/10 b codec function,four channels Alignment function and radiation-tolerent codec function.This thesis implements the 8b/10 b codec circuit based on the principle of 8b/10 b codec.Firstly,the structure design and working mechanism of the encoding circuit and the decoding circuit are determined respectively.The interaction of the important signals between the sub-modules is analyzed.Then the circuit design of the specific codec sub-module is carried out respectively.Finally,it is achieved that an 8b/10 b codec circuit supporting two work patterns: data-width of 16-bit and 8-bit.In this thesis,based on the principle of four-channel alignment circuit,a four-channel alignment circuit is realized.Firstly,the structural design and work pattern of the circuit were determined,then the key module FIFO and state machine were analyzed and designed.Finally,the four-channel alignment circuit is realized,which supports 16-bit and 8-bit work patterns,and 1X,2X,and 4X aligned channels.In this thesis,a new radiation-tolerent codec scheme is proposed for preventing the Ser Des from continuous multi-bit error due to the influence of single-event effect.The principle of the radiation-tolerent codec scheme is introduced,the data transmission and processing process as well as workflow is described in detail.The circuit implementation of the codec scheme,the circuit structure design and working mechanism are respectively described.At the same time,the key sub-module synchronous FIFO,asynchronous FIFO and boundary alignment module in the decoding circuit are introduced in detail.In addition,the advantages and disadvantages of the proposal were analyzed and discussed.The advantages and disadvantages of the proposal and the three-mode redundant circuit are compared.The influence of the proposal on the DC equalization is also discussed.Finally,an contiuous 20 bit error tolerent codec circuit is realized.This thesis also realized and verifed the top design of the anti-irradiation four-channel Ser Des chip including the three functions above and the existing Ser Des IP,which integraed the 8b/10 b codec function,the four-channel alignment function and the radiation-tolerent codec function.In this thesis,the Verilog HDL language is used to coding the RTL-level circuit function design of each module.The simulation platform is built by NC-Verilog to verify the full-chip function,verifying the whole design.