Application And Verification Of PCIE And FC Protocol High Speed Information Transmission Module For SoC

PCI Express bus is a new generation of I/O local bus standard.It is to replace the PCI bus protocol.With the continuous development of technology.PCIe bus has been widely used because of its high transmission bandwidth and the new point to point of interconnection architecture and compatible with the characteristics of the computer platformThis research project is based on the research project of enterprise practice.Project team implements a FC-AE-ASM protocol processing chip for FC nodes based on So C.The communication between the chip and the host needs to be achieved through the PCIe link channel.A large number of data transmission using DMA transmission.This paper specific implementation of the protocol chip PCIe interface module based on project requirements and in-depth study on the basis of the PCIe protocol.This paper adopts the top-down design idea and module division of PCI Express data transmission system.In this paper,we will analyze the PCI Express physical layer in detail,and analyze the serial training,LTSSM state machine and serial / parallel conversion and differential signal generation in the logical sublayer.The paper mainly completes the PCIe transmission interface design and completes the high-speed data transmission through the bus DMA transmission mode.We build RTL verification platform to complete the module-level validation work in the Linux environment.We also use of FPGA test board for FPGA verification,so that hardware and software verification at the same time.This mutual cooperation is better to verification work.Ultimately,through gate-level verification and post-simulation,ensure that the timing is correct after the tape out.The design of high-speed information transmission module through the DMA transfer transmission rate of 800MB/s.