Research Of PLL Circuit In High Speed SerDes

With the development of big data,the high speed Serialization and De-serialization(SerDes)interface,which has gradually replaced the parallel interface,is widely used in SoC integration.Phase Locked Loop(PLL)is an important module in high speed SerDes and provides high perfonnance and low noise clock signal for the core parts,including clock and data recovery(CDR)circuits which focus on low jitter/phase noise and fast settling.As a part of CDR in a high speed SerDes IP,a PLL block is implemented including circuits of phase frequency detector(PFD),charge pump(CP),loop pass filter(LF),voltage-controlled oscillator(VCO),frequency divider(DIV)and duty cycle correction(DCC)in 65nm CMOS process.On the basis of the theory of phase locked loop,the transient response and noise of the loop are analyzed.The design process of the circuit and physical implementation procedure is described.At last,the comparison of simulation and test of the SerDes chip are earried out.The PFD is consisted with RS flip-flops.The output current of CP ranges from 10?A to 80?A,and introduces differential signals to suppress non-ideal effects.The PLL employs a programmable dual-path loop filter with integrating path and novel resistorless proportional path that can be independently controlled and accurately modeled for flexible setting of closed-loop bandwidth and peaking to the different serial links protocols.With the structure consisted of a integral path and a proportional path,resistors in the loop are removed,leading to jitter performance improvement and locking time reduction.The four-stage ring VCO outputs eight phase signals and controls output frequency with transition gates.The duty cycle adjustment circuit makes the duty ratio of output signal 50%.Simulation result is well for PLL block.The maximum input frequency of the signal is 1.35GHz.The mismatch current is less than 1%at 50?A,the frequency coverage range is 500m to 2.5GHz in VCO,Kvco is kept at 4GHz/V to ensure loop stability.The phase noise is-80c/Hz at 1MHz offset from 1.0625GHz output.In the worst case,the loop lock time is less than 4?s and the biggest jitter of Vc is less than 14mv with 10.692mW of power.In chip test,the error rate is qualified and the eyes diagram is clear.