High-Speed SerDes Test Design

As the data rate of wireline backplane communication approaches28Gb/s and beyond, serializer/deserializer (SerDes) IP cores’ test design becomes challenged. It is a difficult problem to test bit error rate and eye diagrams of high-speed SerDes (HSS) IP cores.To achieve the goal of testing eye diagrams of HSS, an eye opening monitor circuitry is designed in this paper. Compared with conventional template-based two-dimensional eye opening monitor (EOM) circuitries, the proposed EOM circuitry can achieve obtaining the size information of eye opening in one unit interval. The experimental results show that the proposed EOM can test12.5Gb/s data rate wireline’s eye diagram with vertical deviation20-mV and horizontal deviation4-ps in TSMC65-nm CMOS process technology.To achieve the goal of testing bit error rates of HSS, a pseudo-random code generation checker circuit is designed. An interface access circuit based on the serial port and JTAG protocol is designed for accessing the HSS status registers. An8-bit parallel generation circuit can run at3.2GHz, and an8-bit detection circuit can run at1.8GHz in TSMC65-nm CMOS process technology.A bit error rate’s evaluation method based on a noise model and a statistical theory is proposed in this paper. The experimental results show that he proposed statistics-based signal-to-noise approach can attain the confidence to95%in the case of3100sample points. The estimation error sample variance is within5%of total variance.In this paper, an eye diagram and bit error rate of HSS’s testing circuitry is evaluated both in qualitative and quantitative approaches. The proposed HSS test design consists of an eye opening monitor, a build-in-self-test circuit, and a noise analysis method, which provides the solution to test HSS IP cores.