622MH_z CCPLL Design Of 0.6μm CMOS Technics

Phase-lock loop loop(PLL) is an important module in analog and mixed-signal circuit, it can track input signal phase and frequency, then it outputs looked-phase, small jitter signal. In system application it can used in lots of field, such as lock recovery , channel select. The des-ign of predominant capability is difficult and pop program in the IC domain at all times.This paper adopts 0.6μm CMOS techniques to designing a charge pump phase-locked loop(CPPLL) which can be used in SDH system. For this designed CPPLL can be applied to two velocity levels SDH system of STM-1 and STM-4, its import signal frequency is 155.52 MH_Z and its export signal frequency is 622.08 MH_Z. Voltage-controlled oscillator is a very important in phase-locked loop,the capability of the phase-locked loop by decided the capability of Voltage-controlled oscillator. In this CPPLL circuit design , a ring voltage-controlled oscillator via current of saturation region tuning, a CMOS capacitively coupled current amifiler be used to a cell of delay. A novel architecture charge pump circuit is proposed,in which the current follow technology is used to make a perfect current matching characteristics, and the charge pump can eliminate the overshoot injection current,clock feedthrough. The phase frequency detector(PFD) module adopts the PFD of dynamic and without die area.We have made a simulation by using the software SmartSpice and 0.6μm mixed signal CMOS techniques parameter, the result shows that the CCPLL have very good capability.