| The system of optic-fiber communication usually adopts phase-locked loop(PL L) to produce the signal of clock. Because timing signal is sensitive to noise and in -terference, the indexes of PLL circuit determine the capability of systems. The des -ign of predominant capability is difficult and pop program in the IC domain at all times.By the developing of fiber communication, Synchronous Digital Hierarchy(SD H) by way of the standard of optic-fiber transmission systems has been applied more and more extensive. The most important and essential velocity of SDH is STM-1, which bit rate is 155.52Mb/s. The higher velocity of STM signal is been gained by the multiplexing of N STM-1 byte. Moreover, CMOS techniques take on the trait of wide voltage work range, low static power dissipation, strong anti-jamming capacity and so on. It is the mainstream technique in the current IC manufacturing. This PLL is used more and more widely.This paper adopts CMOS techniques to designing a charge pump phase-locked loop(CPPLL) which can be used in SDH system. For this designed CPPLL can be applied to two velocity levels SDH system of STM-1 and STM-4, its import signal frequency is 155.52MHz and its export signal frequency is 622.08MHz. In this CPPLL circuit design, we bring forward a new voltage-controlled way, namely presents a ring voltage-controlled oscillator via MOS capacitance of saturation region tuning. Among which the charge pump portion adopts a novel charge pump circuit that can eliminate the overshoot injection current. The phase frequency detector(PFD) module adopts the PFD of dynamic and without die area. We have made a simulation by using the software SmartSpice and 0.6um mixed signal CMOS techniques parameter. The result shows that the locked time of the PLL is 5.2us, the locked range is about 100MHz, the cycle-to-cycle jitter of the output center frequency at 622MHz is about 71ps, and its power dissipation is 19.8 mW. This CPPLL system could work normally from -60 ℃ to 50 ℃... |
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