The Research On BIST Technology And A BIST Scheme For Mixed-signal Circuit

With the rapid development of IC technology, more and more cores are integrated into a chip. How to carry through the effective test looks more and more important.In this thesis, we first introduce the technology of test and the principle of built-in self-test (BIST) of design for testability (DFT). We also discuss the structure of BIST, the class of test method and so on. After illuminating the necessity of low power scheme for BIST and the mode of power consuming, the thesis proposes a new adjustable TPG structure that is targeted to reduce the switching activity during BIST test sessions. We prove that the TPG of this structure will not produce the repeat test pattern, and the character of pseudo-random test will not change. So in the condition of the same test length, the fault coverage of the new structure is quite close to the original one. We reduce the test length by using theory of input compatible and sharing the compatible input.Secondly, the thesis discusses the knowledge of the BIST approach for mixed-signal circuit and previous works of this aspect. Without a large number of precision reference voltages and with the consideration of matching problems, a BIST approach is proposed to test the parameters of DAC, which includes offset error, gain error, differential nonlinearity error, and integral nonlinearity error. The accuracy of offset error test, gain error test, INL error test and DNL test are all beneath 0.20LSB.The INL test accuracy depends on the testing time. The longer testing time, the more accurate is.At last, some calibration circuits to calibrate the errors caused by the analog imperfectness are described and added to the above circuit to improve the accuracy. The circuit is simulated with SMIC 0.35um 1P5M Process, and it is proved that this structure of BIST improve the precision and shorten the time of test. So the result proves that the BIST technology has advantage on the test of mixed-circuit.