Research On VLSI Low Power BIST Based On Folding Counter

Built-in self-test (BIST) technique has afforded a prospective test method to complicated integrated circuits (IC), especially to system on a chip (SOC). BIST can reduce test costs of an IC by eliminating the need for expensive test equipment and test time. In a word, BIST not only circumvents test problems, but also offers the cheaper and more efficient alternative. Therefore BIST has become a topic of major interest in recent years.Usually, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, and decrease of overall yield. Low power dissipation during test application is becoming increasingly important in today's VLSI systems design and is a major goal in the future development of VLSI design.In this dissertation, we put forward two low power BIST test schemes for test power problems. The main content of this dissertation as follows:1 The summarization of low power BIST is described. Several low power test schemes are enumerated, and their characteristics are analyzed and categorized.2 In mixed-mode BIST low power test scheme, the gating of system clock scheme is applied to achieve pseudo-random low power test, and utilize the characteristic of the folding sequences at the phase of deterministic test to gain low power dissipation test. By adjusting the order of these folding sequences loaded, it can improved the correlation of successive vectors. Therefore, switching activities in the circuit under test (CUT) are reduced remarkably. Finally, the mix-mode low power test scheme is accomplished.3 The scheme of complete deterministic low power BIST test is brought forward. Firstly, the minimum set of seeds that LFSR and folding counter encoded the complete deterministic test vectors is acquired. The seeds can stored at ROM in CUT or test equipments. Experiment results show the ratio of the encoding scheme is better than frequency-directed run-length (FDR) codes, and the decoding process of this method is easier than FDR codes. When the seed is decoded, the order of generated vectors by folding counter is adjusted. This aim is to gain higher correlation of successive test vectors. Consequently, higher correlation of adjacent test vectors can actualize low power dissipation in test.