Application Of Folding Counters In SoC Test

With the improvement of process technology and the enhancement of density ofintegrated circuits (ICs), especially after the emergence of SoC, more and more IPcores are integrated into a chip. As a result, the number of target faults in IC testingis rapidly increasing, the volume of test data is surging. Researches show that theincreasing volume of test data brings the increasing test cost.Built-in Self-test (BIST) can test the circuit just using the resources which existson the chip rather than expensive automatic test equipment (ATE). BIST is aneffective method to solve the difficulties in SoC testing. Scan design, which featuresits controllability and observability, is one of the most popular DFT methods.However, each test pattern is shifted serially into the scan-chains, which causes extratransitions of circuit node. The extra transitions bring high test power. High powercauses some problems, such as circuit damages, the degradation of stability andreliability of system, the yield loss etc. The thesis focuses on the great volume of testdata and the high test power.Firstly, this thesis introduces the present situation of the development of IC andthe fundamentals of SoC testing. The reasons for high power in SoC testing and testpower model are presented in chapter2, the low power methods is briefly classifiedand the importance of low power in SoC testing is explained.Secondly, a scheme of low power deterministic built-in self-test based on foldingcounter is proposed, which is a mixed-mode BIST. All scan cells are grouped bycompatible and anti-compatible relationship and controlled by group signal in thescheme to reduced shift power during test.Thirdly, a BIST scheme based on parallel folding counters is presented, whichtakes advantage of constraint input reduction technology, LFSR and parallel foldingcounters. Compare with bi-seed compression scheme, the scheme needs less storagespace, much shorter test application time and lower hardware overhead.