System-on-chip BIST Test Generation Technology Research And Application

With the continuous increase of the integration and complexity of a SoC, theincreasing speed of the quantity of the transistors of an IC is far much quicker thanthat of its pins, and the gap between the inner bandwidth and the outer bandwidthof an IC is becoming more and more enormous, which leads to the phenomenon thatthe traditional outer testing approaches could not meet the requirement for the timebeing. Meanwhile, the SoC is becoming more multi-functional and powerful thanever before by integrating many kinds of IP cores, which results in the fact that thedetecting technology related to the performance of an IC is becoming more andmore important, the fact that the testing process of an IC is becoming more andmore difficult and expensive, as well as the fact that the cost of the generation fortesting takes on an exponent increase. The current cost for testing has alreadyreached more than half of the total cost of an IC, and would also increase year byyear. The feedback information generated by testing has been the unique appro achfor analyzing and locating the defects of any kinds. Furthermore, the testing beyondthe product requires additional processing steps, which may bring new defects to anIC. With the increasing requirements of the reliability, possibility as well as themaintainability of a product, testing has already been a critical restricting factor forthe design and application of a VLSI, especially for a SoC.The technology process of an IC to be tested is more novel than that of anordinary outer testing equipment, while the testing equipment that could meet therequirement is much too expensive. Thus, design for testing is an efficient approachfor reducing the complexity of testing generation and testing cost, in which BIST isan important one. In order to reduce the cost of testing generation, A ParallelFolding Counter based on the selecting state transfer is also proposed. Comparedwith the former, the improved folding counter can eliminate the defect that onlyone bit testing data could be generated in one clock cycle, can generate a completetesting graphic in one clock cycle, and can reduce testing time at utmost.Meanwhile, the testing graphic could be selectively generated based on the foldingdistance to reduce the generation of the redundant testing grap hic and could furtherreduce testing time. The concrete circuit has been implemented and improved, achieving the goal for reducing hardware overhead.The technology for testing generation is studied and the critical technologyLFSR is applied to the transportation of SATA data telecommunication. Scramblingand unscrambling of telecommunication data is an important task for SATAinterface design. This paper studied the theory of scrambling and unscrambling ofdata as well as the algorithm for data scrambling based on m-sequence. Inaccordance with the implementation for the interface of solid state disk SATA, aSATA specification suited LFSR with special primitive polynomial is applied to thedesign and induction of a data scrambler based on m-sequence. The m-sequencescrambling algorithm is applied to the randomly processing and recovering oftransporting data, which could effectively improve the quality oftelecommunication and reduce the bit error rate of data transportation. Theexperimental result of simulation and synthesis shows that the designed scramblercould meet the telecommunication interface requirement of the solid state diskSATA, could effectively scramble and unscramble data, and could meet therequirement for a low hardware overhead as well as use in common.