Seedy Digital Circuits Built-in Self-test And Test Complex Research

With the rapid development of IC technology, more and more cores are integrated into a chip. How to carry through the effective test looks more and more important.First of all, the basic knowledge of digital system test and the principle of Built-in Self-Test (BIST) are introduced in this paper. The author uses the C program to finish the parallel fault simulation that is used to calculate the fault coverage.Secondly, the reseeding built-in self-test technique based on scan that has wide application nowadays is studied in this paper. In BIST reseeding with very few seeds, a seed corresponds to more than one deterministic patterns, which can reduce the number of seeds that need to be stored and the test hardware overhead. The explored multi-phase reseeding technique fully exploits the encoding ability of an LFSR (linear feedback shift register) seed by using more than one cells of the LFSR for feeding the scan chain of the circuit in different test phases. The paper introduces the choice of the length of the LFSR, the feedback polynomial and the corresponding cells in detail. The above two techniques are realized by C program. Experiments are done on five idiographic circuits, and the results are given. Comparing the results, we can see the multi-phase reseeding technique has superiority in test hardware overhead and the length of test sequence.Finally, sharing test pattern generation is studied. To test all the logic cores on a system-on-a-chip using a unique ROM to store the seeds and a unique LFSR to produce all the test patterns., a technique uses a LFSR to produce the pseudo-random patterns and to encode all the deterministic patterns, so all the logic cores can share the test logic and can reduce the test data storage. Two reseeding built-in self-test technique based on scan researched above are used in the sharing test pattern generation. The test of a system composed of five circuits is simulated.