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The BIST Design And Implementation Of Onboard Processor Pipeline

Posted on:2008-09-14Degree:MasterType:Thesis
Country:ChinaCandidate:X B ChenFull Text:PDF
GTID:2178360242998746Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
In the space radiation environment, the on-board microprocessor semiconductor devices occur single event effect easily and led the microprocessor to bring failure, which serious impact on the reliability and lifetime of spacecraft or satellite. When the on-board microprocessor has a fault, it needs a low-cost, efficient way to achieve how to judge fault, locate fault, remove fault in multi-core processors.As one of the sub-topics of the school's preliminary research project "under the harsh environment on-board processor systems technology research", the thesis studies the mechanism of BIST deeply, sums up the processor pipeline BIST methods in theory derivation and on the basis of building model, and realizes the device overhead and fault coverage on the compromise. The thesis verifies the correctness of BIST by injecting fault in modelsim simulator, calculates and evaluates the cost and fault coverage of BIST design through theory. Among the research results include the following points:1 .On the basis of preliminary analysis of the current on-board microprocessor technology, the research proposes BIST based processor pipeline design strategy,which studies the BIST theory deeply, and combinates the two features, against its high reliability requirements.2.With Leon3's existing pipeline technology, the design creativly makes the BISTdesign based pipeline, considers efficiency and price comprehensivly, and the pipeline is nested on the use of BIST, which greatly reduces the cost.3. The thesis researches, analyzes the LEON3 source deeply,describes the BIST design with VHDL in the LEON3 source, and completes the LE0N3 simulation by using ModelSim after joining BIST, and completes the LEON3 synthesis by using Synplify after joining BIST.4.The thesis researchs integration of systems logic and built-in-self-test logic, integrates built-in -self-test logic in the original structure of the system, and achieves combination of built-in self-test logic with the system logic (the department is the original logic other than built-in-self-test logic) as perfect as possible, through simulation and soft fault injection, the design fulfills the realization of the fault detection, fault distinction, fault location, and so on.5.Through theoretical calculations and the cost analysis,with few consumption of resources , the rate can be tested to reach 99% when a fault is in its microprocessor.
Keywords/Search Tags:Seven Pipeline, LEON3, Integer Unit, Built-in Self-Test(BIST), Multi-input Signature Register(MISR), Fault coverage Rate
PDF Full Text Request
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