The Study On Built-in Self-Test Method Based On Multi-Scan Chains

A large number of functionality can be packed into a chip, which is called sytem on chip. With the increase of IP Cores, the functions of SoC are becoming more and more complicated, and the test data volume and test power consumption are sharply increasing, and test equipment becomes more expensive, thus the greater challenges occur in SoC test. By moving test generation, application and test response into the chip itself, BIST eliminates the need for high speed automatic test equipment, reduces the test cost and can provide at-speed testing. In this thesis, the problems of the multiple scan chains BIST logic simulation-based Phase Shifter algorithm and mixed-test mode are studied.First of all, several methods about testing technology and design for testability and SoC test techniques are summarized. And then, against the logic BIST test pattern generation of exhaustive testing, exhaustive testing,pseudoexhaustive testing, pseudorandom testing, weighted testing and "store and generate" testing are described in brief.Phase shifter can reduce the data dependeney among scan chains during pseudorandom testing and plays an important role in the improvement of fault coverage for cireuits under test. In this thesis a logic-based simulation algorithm phase shifter is improved. In this improving algorithm, the properphase shifter selection vectors can be obtained by simulating N-stage Linear Feedback Shift Register 2~n-1 cycles. The selection vectors, which are obtained by this method, reflect the components and distributions of value cells clearly, thus avoid a number of forward and backward simulations of dual LFSR, vectors output order are adjusted for reducing the test power loss. Compared with the experiment results, the proposed method shows its effectiveness. The fan-out flip-flop is balanced and the test power loss is reduced.In this thesis, to improve the fault coverage, storage-mode is added to LFSR-mode. In the storage-mode, a accommodating data reseeding Built-InSelf-Test way by selecting multiple-cell is proposed. LFSR ability to make full use of the code produce the best seed. And the use of test vectors compatible compression to reduce the concentration of the test is indeed included in the median position, reducing the complexity of calculating LFSR seed and the seed-digit. A modified structure with Test-per-Clock and test-vector compression reduces the testing time. It shows the means enhances the effect of LFSR coding by experiments and improves the fault coverage.