FPGA Implementation For The Digital Pulse Compression And CFAR Detector

In recent years, the rapid development of CPLD/FPGA has been one of the most important technologies of realizing digital signal processing. In this paper, it focuses on the hardware implementation of two modules of signal processing by FPGA, which are digital pulse compressing system and GO-CFAR detector. In the first part, we present the fact that digital pulse compressing is one of the most important technologies in modern radar. The module of FFT is the core of the hardware implementation of pulse compressing. Then the basic knowledge of FFT and the detail design of digital pulse compressing based on IP core of FPGA are introduced. The simulation result, simulation waves and the comparison of simulation of software are presented. In the last, it gives some optimized advises about design. In the second part, we also point out that CFAR (Constant False Alarm Rate) detector is an important part in the field of radar signal detector and several methods are illustrated theoretically which can realize the CFAR processing. Then, the design method of GO-CFAR detector by FPGA is present and the implement of each module of detector was introduced.