FPGA-Based Implementation Of Pulse Compression Processor Of Software Radar

As a kind of high-density special digital integrated chip configured by user, Field Programmable Gate Array (FPGA) has many advantages, such as miniaturization, low power dissipation, programmable logic, digitalization and velocity. FPGA has developed into important device for signal processing from a kind of flexible platform for logical design, since it's flexible and high-speed. FPGA has been applied extensively in many software radio productions.Software radar is the result that software radio technology with opening structure is applied to modern radar design. As a typical architecture used in modern software radio systems, the structure combining FPGA with multi DSP is the same with designing software radar. Its main benefits are flexible structure, adaptability, easy maintenance and extension and real time signal processing. Higher-level processing algorithms are fit for implementation in DSP which has high operation rate, flexible addressing mode and powerful communication system, since their control is complicated. On the other hand, lower-level processing algorithms have simple operating structure. At the same time, they process a great deal of data with high rate. These characteristics make them suitable to realize in FPGA.Pulse compression technology has request of multi-channel and real-time processing when it is applied in software radar. It can be implemented in FPGA because of its simple arithmetic. The practical application background of this paper is"High Frequency Software Radar"which is one of Country"211 projects"key discipline items of basic construction. The object of this paper is the implementation of 16 channel real-time pulse compression processing in FPGA which is integrated on digital receiver board named ICS-554. Two additional functions are realized in FPGA. One is deleting pipeline delay of ICS-554 and digital stimulator named ICS-564, the other is device recognition of ICS-554.Firstly, this paper submits three implementing method of pulse compression processor after analyzing signal form used in system. According as design index requested by physical system and FPGA resource status, this paper compares relative merits of three plan and determines to use MAC method in time domain. In this method, single MAC operation module is used by time-sharing to complete 16...