The Research Of Digital Down Conversion And Digital Pulse Compression Based On FPGA

Digital Down Conversion(DDC) and Digital Pulse Compression are used widely in pulse radar receiver. Digital Down Conversion eliminates the signal carrier frequency after sampling in order to process signal in the baseband. As the one of the most important techniques in radar algorithm, Digital Pulse Compression resolve the conflict between radar range resolution and transmitting distance. With the development of large scale integrated circuit, algorithm of signal processing in radar receiver goes forward from DSP(Digital Signal Processor) to FPGA(Field Programmable Gate Array). Studying Digital Down Conversion and Digital Pulse Compression based on FPGA is not only the important content of digital radar but also increase signal processing speed and release the precious resource of DSP.The paper studies every unit at first which compose the DDC system, including band pass sampling theorem, mixer NCO(Numerically Controlled Oscillator), decimate filter CIC(Cascade Integrator Comb), FIR filter. Then research some knowledge which is necessary for building Digital Pulse Compression system, including matching filter, time and band product and Digital Pulse Compression of Chirp signal. The paper analyzes the algorithm of the units of DDC and chooses the proper one form the Digital Pulse Compression scheme then studies FFT( fast Fourier transform) primarily. It designs hard circuit and builds the systems with VHDL language programming and IP core then uses Matlab to analyze the simulation wave from QuartusII. The design experiments on the hard circuit reads the results from DSP, contrasts with the simulation wave and analyzes the source of error at last.The system can content project according to the experiment and have real time, extensible, flexible features.