Research On The Clock Recovery Chips In 10Gbit/s SDH/SONET And 10-Gigabit Ethernet

The development potential of the network cannot be simply evaluated. For one side, the optical fiber transmission bone network is now upgrading to the 10 Gbps of the STM-64 /OC-192 SDH/SONET. On another side, the Gigabit Ethernet (GbE) and the 10 Gigabit Ethernet (10GbE) is now getting mass application in the public digital communication network. The explosive growth of the digital communications services has fueled the requirement for semiconductor integrated circuits that support ever-increasing data rates. The clock processing circuit is one of the key bottlenecks of the speed elevation. This paper introduces the system structure of 10Gbit/s Ethernet systems and submits several circuit target. According to principle of clock recovery, the paper also gives a detailed analysis of Phase-Locked Loops (PLL) among different circuit realization which is currently the most used technique, including its several design ideas. At last, after analyzing result of the senior, the design of the circuit, simulation result, design of the layout and the plan of the test is concerned in the paper.Phase noise as a very important characteristic is described in detail, including the contributions of noise in PLL cells to the whole loop, phase noise analysis of VCO, method of improvement, etc. In order to reduce the complexity of the circuitand and to improve the quality of design, the preprocessor is designed finely.This project is supported by the"National-High-Tech-Program"(863 Project), the project is research on the key chip in 10—40Gb/s optical transceiver(Cont.).