The Clock Processing Chips Design Of 10-40gbit/S Sdh/Sonet,10-Gigabit And Gigabit Ethernet

The development potential of the network cannot be simply evaluated. For one side, the optical fiber transmission bone network is now upgrading to the 10 Gbps of the STM-64 /OC-192 SDH/SONET. On another side, the Gigabit Ethernet (GbE) is now getting mass application in the public digital communication network, and the 10 Gigabit Ethernet (10GbE) standard has also been released. The explosive growth of the digital communications services has fueled the requirement for semiconductor integrated circuits that support ever-increasing data rates. The clock processing circuit is one of the key bottlenecks of the speed elevation.The clock processing circuit includes the clock generator unit (CGU) of the transmitter and the clock recover circuit (CRC) of the receiver. Phase-locked-loop (PLL) is currently the most wildly applied technique in CGU and CRC.Based on the analysis of charge-pump PLL (CPPLL), the CGU of 10 Gbps optical transmission system, GbE.and 10 GbE are designed and simulated and a monolithic clock generator/multiplier chip for GbE type 1000BASE-X has been realized and characterized. As the key circuits in the clock processing chips, a 3.125 GHz fully integrated CMOS ring voltage controlled oscillator (VCO) chip and a 7.2 GHz completely integrated PLL chip are also brought forth.CRC is one of the most difficult parts in the design of physical layer processing circuits. Through the analysis of traditional CRC and its shortcoming, this paper also puts forward a new technique to broadly spread the lock-range and minish the steady- phase- difference of the analog PLL. Using the new technique, a new type of high compatibility dual-loop CRC structure is given and a fully integrated 10 GHz dual-loop CRC chip compatible with STM-64 /OC-192 SDH/SONET and 10GbE 10GBASE-R/W is realized and characterized.The measure results show that the chips not only fulfill the basic function but also have good performance.