.10-40gb / S Optical Communication And Gigabit Ethernet Clock Generation And Recovery Circuit Design

The demand for high speed and large capability transmission systems has been on a great upsurge with the progress in the technology of information and network. Under such circumstances, researches on optical transmission IC and 10Gbit/s Ethernet become more and more heated.This paper introduces the system structure of 10Gbit/s Ethernet and optical transmission systems and submits several circuit target. According to principle of clock generation and recovery, the paper also gives a detailed analysis of Phase-Locked Loops (PLL) among different circuit realization which is currently the most used technique, including its several design ideas. Phase noise as a very important characteristic is described in detail, including the contributions of noise in PLL cells to the whole loop, phase noise analysis of different kind of VCO, method of improvement, etc. In the foundation of above theory, the paper gives the circuit of 10GHz clock generation and the circuit of 40GHz PLL. In the circuit of 10GHz clock generation a clock of 10.125GHz is derived from reference clock of 644.53125MHz and its jitter is less than 100ppm. 40GHz PLL is used in clock recovery module of 40Gbit/s optical communication receiver and is desired to manage NRZ signals. Both of these two circuits use GaAs PHEMT Technology and the theory of transmission line in microwave. The simulation results of 10GHz clock generation and simulation results of 40GHz PLL are given subsequently and the last chapter indicates conclusion.