The Integrate Circuit Design For 10-40Gb/s Optical Communication And 10 Gigabit Ethernet Clock-Recovery

As the optical communication has developed to 40Gb/s and the SDH64/192 with 10 Gigabit earthnet together are heading for application, it is crucial to design the related integrate circuit with self-owned intellectual property rights as soon as possible. Clock recover circuit (CRC) is pivotal and indispensable for receiver system of communication. The paper discusses the principles of CRC and the frameworks of some familiar CRCs, and introduces the design of clock recovery circuit based on a phase-locked loop. The PLL technique utilized widely in CRC is analyzed in detail, and a fully integrated LC VCO with 40GHz oscillator frequency is also presented.In the design of high frequency VCO, coplanar waveguide (CPW) is used as inductor.A phase noise of -103dBc/Hz was simulated at 1MHz offset from a carrier frequency of 40GHz.All of the circuits are realized in 0.2μm GaAs PHEMT process with a 3.3V supply. The measurement of the test chip shows that the VCO in the CRC has a wide tuning range and a low phase noise.To explain the importance of the process in circuit design, technics of some sorts of IC in common use with emphasis on the characteristic of GaAs PHEMT process are elaborated in one chapter of the paper. It is effectively decrease the parameters in key point by arranging the devices according their models.