The Design Of Wide-range All Digital Successive Approximation Register-controlled Delay-locked Loop

With the rapid development of semiconductor technology, the CMOS transistorswhich can be integrated in a chip has as many as2.3billion, and as a result,theintegrated circuit chip is developing toward the system-on-chip (SoC)。The SoC hasmore and more high requirements in the working frequency。Undoubtedly, in the ageof the gigahertz working frequency? the clock skew has become a bottleneck of SoCdevelopment。Dday-locked loops (DLLs) have been widely adopted in a variety ofintegrated circuit chips to minimize the clock skew. At present, all digitaldelay-locked loops can be divided into three kinds: Register-controlled Delay-LockedLoop (RDLL),Counter-controlled Delay-Locked Loop (CDLL) and SuccessiveApproximation Register-controlled Delay-Locked Loop (SARDLL). SARDLL is paidmore attentions for its shorter lock time. However, due to the conventional SARDLLadopting differential signal delay cell, it has a very narrow range of workingrfequency. Meanwhile, it is not realized using digital design lfow because of thecustomized capacity. On the basis of conventional SARDLL,a improved wide-rangeSARDLL is presented in this paper by using the standard logic gate to construct thedelay cells.We chose the EDA tools to construct an implementation platform reasonably,anduse the SMIC CMOS0.18(im1P6M process to implement the improved all-digitalSARDLL. Under the typical situation, the improved SARDLL has been simulated intransistor level using HSIM simulator, and the simulation results show that the lockedrange is rfom200MHz to670MHz.