Research Of The GHz Low-Jitter Fast-Locking Phase-locked Loop

As a negative feedback system,phase-locked loop circuits can produce accurate frequency signals to ensure the correct signal processing.And thus the phase-locked loop circuits have an important position in radio frequency wireless communications,high-speed wired communications,optical fiber communications,high-performance digital circuits and other application fields.With the rapid development of integrated circuits and the continuous improvement of data transmission speed,people desire phase-locked loop circuits with better characteristics,such as clock jitter,lock time,power consumption,chip area and so on.Thus,designing a phase-locked loop circuit with low clock jitter,fast lockout and wide output frequency range becomes the current trend and challenge.This thesis mainly studies the phase-locked loop circuit used in frequency synthesizer.Firstly,the working principles,basic structures of phase-locked loops are analyzed,as well as the frequency synthesizer performance.Then,the system design theory of phase-locked loop frequency synthesizer is studied,and the phase-locked loop linear(S-domain)model is established to analyze the dynamic characteristics and stability of the loop.Based on this work,the high-order loop filter is designed.Then,the noise characteristics and clock jitter of the phase-locked loop are considered from the system level.Based on the linear invariant model,the transmission function of the noise sources in the circuits is deduced,and then the noise performance is optimized at the system design level.After the theoretical analysis of the system,the key building blocks of the frequency synthesizer has been deeply researched and designed.In this paper,the delay time of the PFD circuit is increased to reduce the effect of death zone.The CP circuit adopts the active operational amplifier to improve the current charging and discharging matching degree.Third-order loop filter is used to get more efficient noise suppression at high frequencies.And the LC-VCO structure helps to achieve better phase noise performance.A wide range of integer frequency division is implemented by use the current mode prescalers and programmable frequency dividers.Based on SMIC 0.18?m process,this thesis designs a phase-locked loop frequency synthesizer for IEEE802.11 a communication protocol.This chip has a power supply voltage of 1.8V and the input reference frequency is 10 MHz.Simulation results show that the frequency lock range achieves 5.15-5.35 GHz and the loop lock time is less than 60?s across the output frequency range.The phase noise of this chip is better than-120 d Bc/Hz at 1MHz offset.Measurement shows that the integral phase error of this frequency synthesizer is 1.08° and the clock jitter is 0.57 ps.This chip has a power consumption of 58 m W and occupies a chip area of 640?m * 640?m.