The Design Of PDRO With Low Phase Noise At C Band

With the development of radar and wireless communications, the request for the local oscillator is higher and higher in the system. Seeking the oscillators with lower phase noise, more highly pure spectrum and more highly stabilization has became the trend to develop.PDROs and DROs are applied abroad to frequency synthesizers and microwave oscillators because of their excellent phase performance, spectrum purity and stability. DRVCO is the most important part in PDRO circuits.At present in DRVCOs the type of reflect-in series and the parallel-connection reflection type are quite common, but the latter excels the former in the field of phase noise. This task is designing and implementing one low phase-noise frequency source at 7.6GHz.Because of good performance of DRVCO of parallel-connection reflection type in the field of noise, the author designed and implemented one PLL frequency source which contains DRVCO of parallel-connection reflection type at 7.6GHz.For reducing the difficulty in designing, the author emulated and optimized the DRO with Serenade8.71 from Ansoft Company. And then designing the PLL, We choose sampling phase detectors in the circuit of PLL. Sampling Phase Detectors have lower phrase noise comparing with digital detector. finally debugged the hardware to get the final circuit. First, the paper analyzes the oscillator's operational principle, classify and noise theory. Then, the paper introduces the phase-lock loop, including its working theory, the design of the loop filter and noise. In the following chapter, some kinds of dielectric resonator oscillators,esp, their operational principle, are introduced. And then the paper expatiates the design, emulation and the implementation of hardware of the DRVCO in this task, and the design and debugging of the PLL. The realizing method of the low phase noise is analyzed and the conclusion is also given. Finally some measure are given to improve disadvantage of the circuit.