| With the development of communication technology,the traditional I/O interface has been unable to solve the problem of fast transmission of signals under low power consumption,while low voltage differential signal(Low voltage differential signal,LVDS)transmission technology uses high-speed differential low swing Amplitude signal transmission has the advantages of high speed,low power consumption,low noise,small area,high integration,low bit error rate,low radiation,strong compatibility and versatility,and can well meet the current high-speed and high-precision data Transmission requirements.As an important module in the LVDS interface system,the phase-locked loop module is responsible for providing a stable and accurate on-chip clock for it.The quality of its phase noise seriously affects the accuracy of data sampling.In addition,lock time and other key indicators of phase-locked loops have also attracted much attention during design.Based on this background,this paper designs a fast-locking low-phase-noise charge-pump phase-locked loop.The core contents include:1.This paper introduces the working principle of the charge pump phase-locked loop and the main performance indicators;The noise characteristics of the core modules of charge-pump phase-locked loops such as voltage-controlled oscillators are analyzed,and the phase noise transfer functions of each component module to the phase-locked loop system are derived,and a feasible method to reduce phase noise in actual design is proposed.Finally,the linear model of each component block of the phase-locked loop and the Veriolg-A model of each module are expounded,and the system-level modeling and simulation of the phase-locked loop are completed based on the above model.2.Based on the traditional charge-pump phase-locked loop,this paper proposes an adaptive fast lock structure to further optimize the lock-up time of the charge-pump phase-locked loop,that is,the method of charging the capacitor in the low-pass filter through the adaptive fast-lock circuit to quickly reduce the control voltage of the voltage-controlled oscillator to near the lock-up level,and the lock-up time of the charge-pump phase-locked loop is shortened from 7μs without the fast-lock structure to 1.5μs,which is reduced by 78%,and the lock-up time is significantly shortened.3.Aiming at the problems of frequency detector,non-ideal factors of charge pump and traditional ring oscillator,this paper adopts an improved phase detector to solve the problems of dead zone and switching delay mismatch of charge pump;The improved charge pump is adopted,on the one hand,it overcomes the non-ideal factors of the charge pump itself,and on the other hand,the output current of the charge pump is configured to be controllable,so as to avoid the loop stability and output phase noise problems under different processes,voltages and temperatures;An improved ring oscillator is adopted,which consumes less power and better phase noise than traditional ring oscillators,with a phase noise of-107.5d Bc/Hz at a frequency offset of 1MHz.This paper completes the design based on TSMC 0.18μm 1P6M CMOS process.The core area of the phase-locked loop chip is 250μm×150μm(0.0375mm~2).The post-simulation results show that under the working voltage of 1.8V,the self-adaptive fast locking is adopted,and the locking time of the phase-locked loop is only 1.5μs,and when the output frequency is 768MHz,the phase noise shows a good level,reaching-100d Bc/Hz@1MHz,and the power consumption is 3.6m W. |
