Design Of 12 Bits 200MS/S High SFDR Current-steering DAC

With the extensive application of communication systems, it has become a trend to increase the data transfer rate and to increase the signal bandwidth. As the dominance of digital communications, Digital-to-Analog Converters (DAC) have become an indispensable module in modern communication systems. High-speed and broadband is the development direction of DAC design technology, which is consistent with the trend of communication systems.High-speed and broadband require that DAC should have good frequency characteristics. Spurious free dynamic range (SFDR) is the main indicator to measure DAC's frequency characteristics. Current-steering structure is commonly used in high-speed and broadband DAC. Based on this structure, by analyzing the factors that impact current-steering DAC SFDR, a conclusion is drawn: the frequency characteristics of current source switch unit output impedance is the major factors which limit SFDR. In view of this factor, a high performance current source switching circuit is designed to improve the SFDR.SMIC0.18um CMOS process is used to design and simulate 12-bit 200MS / s current steering DAC with high SFDR. When the input signal frequency is 1MHz, 10MHz, 50MHz or 100MHz, signal distortion ratio (SNDR) are respectively 74dB, 73dB, 70dB and 67dB; effective number of bits are respectively 12,11.9,11.2 and 10.8; SFDR are respectively 93dB, 83dB, 71dB and 68dB. Compared to the same kind of papers published in China in recent years, the result of SFDR simulation in this paper is better. The requirement of high SFDR in this subject is achieved. The settling time of the overall circuit is 2ns, power consumption is 23mW, and layout area is 0.4mm2.