Design Of High-speed And Low-power DACs For Broadband Communication Systems

The improvements of communication system performances are always supported by the fast progresses of integrated-circuit technologies. In next- generation communication systems, it has been the trend to increase the bandwidth of signals and thereby enhance the transmission data rate. On the other hand, with the prevalence of mobile communication devices, reducing the power dissipation of communication terminals has already been an important design issue. Due to the dominance of digital communication systems, the digital-to-analog converter (DAC) is a significant module in modern communication systems. Correspondent with the communication systems, the DACs also have the trend to be higher in speed and lower in power dissipation.In broadband communication systems, the performances of the DACs and the analog-to-digital converters (ADCs) often become the bottleneck of the system performance, and it has been one of the most urgent demands in broadband communication systems to improve the performance of high-speed DACs. To meet the urgent demand, this thesis has studied the design issues of high-speed and low-power DACs in broadband communication systems, and accomplished the design, tape-out and test of such a DAC chip.The high-performance DACs applied in broadband communication systems usually adopt the current-steering architecture. Some detailed analyses have been given in this thesis on how the circuit imperfections in the DAC influence the spurious-free dynamic range (SFDR) performance. Based upon the analysis results, a novel current switch and a novel synchronization latch have been proposed. The SFDR with a high-frequency input signal has been improved effectively by applying these two novel circuits in the DAC design. Also a number of other design techniques have been applied in the DAC design to suppress various error sources in the integrated circuit. In the DAC design of the thesis, the demand of low power dissipation has been considered in all the sub-circuit designs. Along with that, the thesis has proposed a complete power management system. The DAC can be controlled to enter standby or power-down status when its normal operation is not needed by the communication system. By power management the average power dissipation of the DAC has been reduced effectively.Besides the complete presentation of the design and tape-out of the DAC chip, the thesis also presents the test scheme of the DAC and the design of the test board. Most of the DAC's important specifications have been achieved in the test, and the test results show that the DAC design in this thesis has approximately achieved the design objectives and the performances are close to those of the designs in recent years'IEEE journals and conference proceedings.