Design Of 12-bit Current Steering DAC Based On RRBS

With the extensive application of wireless communication systems,it has become a trend to increase the data transfer rate and to increase the signal bandwidth.As an important part of the system,the Digital to Analog Converters(DAC)needs to meet its signal bandwidth and frequency characteristics.Since the current steering DAC has the advantages of intrinsic high speed characteristics and good driving capability,it has been widely used in wireless communication systems.However,as the sampling clock frequency and the input signal frequency increase,the dynamic performance of the current steering DAC is affected by timing errors,output ripple effects,and switching transient nonlinearities.Therefore,under the condition of satisfying high-speed broadband,it is imperative to improve the spurious free dynamic range(SFDR)of DAC.From the practical application point of the wireless communication chip,this paper firstly analyzes the factors that lead to the decrease of the SFDR in current steering DAC.Then based on the Random Rotation-Based Binary-weighted Selection(RRBS)method,and this paper designs a 12 bit current steering DAC that is adapted to the wireless communication chip.For the input signal of the DAC,the adopted RRBS circuit completes the corresponding current output by randomly selecting a unit current source at different positions each time,so that the fixed relationship between the input signal and the current source error is randomized,causing the harmonics associated with the input signal to be converted to random noise,which achieves the goal of improving the SFDR of the current steering DAC;In addition,compared with other correction methods,the RRBS method has less logic complexity,and requires less chip area.Based on the SMIC 0.18?m CMOS process,this design uses Cadence's Virtuoso platform to complete the 12 bit current steering DAC circuit design,layout design and simulation.The layout area of the entire circuit is about 0.69 × 0.41mm2.The post-simulation results show that the setup time of the whole circuit is 4ns,the range of DNL is ±0.38 LSB,the range of INL is ±0.85 LSB,the SFDR is 83.74 dB when the sampling clock frequency is 100 MHz and the input signal frequency is 1MHz;the DAC achieves a SFDR better than 65 dB at 49 MHz input frequency,which can meet the frequency domain requirements of wireless communication chips for DAC.