The Research Of SoC Test Data Compression Based On Data Block Coding

The emergence of SoC technology brings a revolution to the design of the VLSI, through reuse a lot of independent intellectual property (IP) cores, chip design cycle is greatly shortted, the speed to market is accelerated, and the output increases correspondingly. Due to the development of SoC, the integration of the chip increase rapidly, the complexity of chip testing and test data volume also increase, while the storage capacity, frequency and the band of the traditional ATE are very limited, these make SoC test facing some problems, such as the time of test is too long, the difficulty and the costs of test increases rapidly and so on.Presently, test data compression technology is an effective solution to these problems. It can be used to simplify the implementation of the test, reduce the test implementation time and lower the test costs.In order to give full play to the features that the don't-care bits in the test set are plentiful and the number of them in each test vectors are by large difference, this dissertation presents a new method based on statistic relativity of variable length data blocks, for each test vector, use the thought of statistics and relativity of data blocks, determine the referenced data block of it, then compress the vector by the relativity between its data blocks and the referenced data block. Besides, the length of referenced data block is independent from each other, at the same time, the referenced data block of each vector has the characteristics that it has the highest frequency of relativity and the least code. The proposed method uses the divide and rule tactic with different vectors to break the constraints in the entire test set. Compare with most of the existing method, it can compress the test set more efficiently, and the decompression architecture is relatively simple, so the applicability of this method is better than others.After that, a new fixed length test data compression method based on encoding the data blocks which are sequential or non-continuous is proposed, with intent to improve the efficiency of the code, view the test set as a number of '0' sequences and the ' 1' sequences, the sequences length over the selected block length k will be seen as sequential blocks, a binary code with fixed length is used to express the length information of the sequential block. On the other hand, the sequences which has lack of it-length is made to be non-continuous data blocks by some strategy, and not be encoded, so it can avoid the situation that short sequences replaced by long code. The rule proposed by the method reduces the complexity of encoding which makes use of prefix and tail code separately, so the process of it's encoding and decoding is simple, and the protocol of communication is also simple. Experiments have been done in the original and precomputed difference test set of ISCAS-89 benchmark circuits, the result shows that this method can receive a higher compression ratio, the decompression architecture designed can decode the compressed test set to original test set accurately, so the method proposed has much more applicability.