Design And Implementation Of The 5Gbps Clock Data Recovery Circuit In 0.13μm CMOS Technology

The demand on I/O bandwidth drives the conventional parallel bus to transfer to the high-speed serial bus gradually. The Clock and Data Recovery (CDR) circuit is crucial in achieving the high-speed link technique. It recovers the synchronous clock from the serial data stream and eliminates the jitter introduced in transmission through data recovery. Therefore the performance of the transmission system is determined by the CDR.In this thesis, the structures of the Over-sampling CDR and the CDR's Jitter Tolerance Bandwidth have been researched deeply. The degradation of the system performance produced by multiphase clock generator's jitter in CDR has been analysed. Based on the theoretical analysis, a 5 Gbps Over-sampling based CDR has been designed and implemented meet the requirement of PCI Express 2.0.The contribution of this thesis includes:1. A 5Gbps CDR is designed and implemented in 0.13μm CMOS technology. The simulation results of Hspice demonstrate that the designing functions of CDR are correct and can fully meet the requirements of PCI Express.2. A 30-phase 500MHz DLL is designed and implemented in 0.13μm CMOS technology. The dynamic interpolation is introduced to diminish the process restriction. The simulation results show the DLL can meet the requirement of multiphase clock in Over-sampling based CDR.3. Aiming at the requirement of static phase error, a new Phase Detector is proposed. It solves the problem of dead zone in Charge Pump's switch transition and also has the ideal features of linear Phase Detector. Meanwhile, the static phase error caused by current missing match in Charge Pump is eliminated.4. A Voltage Controlled Delay Line and A Charge Pump are optimized for stabilization of sampling system. Jitter of the DLL's output has been reduced and performance of the CDR has been improved.