Study On 10-Bit High-Speed Pipelined Analog-to-Digital Converter

With the great development of wireless communication, analog-to-digital technique, which is one of the key techniques in wireless communication, is being made amazing progress due to the more and more demand from products. After more than thirty years of research and development, ADCs have realized the highest resolution of 24bit and the fastest speed of 40GSample/s. Various ADCs are capable of meeting the needs of nearly all applications. Pipelined ADCs, one of the most popular ADCs, are mainly used in those fields which look after both resolution and speed, such as wireless LAN in communication, cell phone and high-resolution digital TV in custom electronic products.In present dissertation, a 10bit pipelined ADC is designed for transceiver of wireless LAN. Main work of this dissertation includes ①By analyzing a great deal of pipelined ADCs, a 5V 10bit 40Msample/s pipelined ADC with the structure of nine 1.5bit-resolution stages is designed. ②Analyze the noise and error in pipelined ADCs. To reduce those errors, several methods are brought up which include using digital correction to enhance the headroom of comparator offset, adopting bootstrapping CMOS switch to improve linearity, utilizing bottom-plate sampling to reduce charge injection and interference between pipelined stages. ③Design a bandgap voltage reference circuit and a voltage-modifying circuit to provide precise voltage and current reference for the referred ADC.Another work is to fabricate the designed ADC circuits in TSMC 0.35μm CMOS n-well process, and test the static and dynamic performance of the chip. The work includes ①By analyzing the testing standard, theory and method of ADC, a set of testing scheme is designed. ② Static and dynamic parameters of the referred ADC are measured by carrying out the testing plan. Experimental result shows that the ADC acquires INL of 3.6LSB, DNL of 0.8LSB, offset of 0.09%, gain error of 5%, power less than 300mW. At 1MHz input frequency and 40MHz sampling frequency, ADC acquires SNDR of 48.2dB, SFNR of 58.2dB, SNR of 48.8dB, ENOB of 7.83Bit, THD of -57dB, At 14MHz input frequency and 40MHz sampling frequency SNDR of 44.4dB, SFNR of 55.1dB, SNR of 45.1dB, ENOB of 7.11Bit, THD of -53dB. The chip occupies an area of 4 mm2.