| Phase-Locked Loop (PLL), which works as a clock synthesizer, has become a necessary and core part in modern microprocessors. It works on the top of the clock tree. Its performance directly influences and decides the highest frequency and stability of the whole chip. The higher the clock frequency is, the more PLL influences the performance of microprocessors. PLL technique has been one of the core techniques in modern microprocessor design.Two kinds of PLL are working in microprosessors today: mixed-signal PLL and digital PLL. Attaining continuous regulation of frequency, mixed-signal PLL has not only very high precision but also wide use. But it has some difficulities in designing this kind because the analog circuit must be achieved under digital techniques. Digital PLL is relatively easier to be designed, but it has lower regulation and precision. It is only applied in some lower-frequency microprocessors today.While the working frequency of microprocessors has reached 3GHz abroad (means the PLL in it can work in at least 3GHz), the frequency of domestic PLL with high-performance is still under 400MHz. So the PLL design technology becomes one of the bottlenecks for the design of domestic microprocessors. It is extremely urgent to have independent high-performance PLL with intellectual property. This article studies the relevant theories and key technology of mixed-signal PLL with high performance and designs a new kind of programmable PLL. The main content includes:1, It studies the mathematical models and working mechanisms of the charge pump PLL (CPPLL) with high-performance. And also studies the steadily control theory of CPPLL. Focused on the "dead lock" state, this article proposes some rapid reset methods.2, It studies the design technology of PLL under digital CMOS technics, studies the parasitic effect of CMOS device on PLL performance and how to compensate it, and studies the implementation methods of the key part of PLL, especially the high-accuracy design technique of the voltage-controlled oscillator.3, It studies the noise mechanism and its impact on loop stability of PLL circuits and obtains some noise reductive measures, which have proved to be better.4, It studies the design method and simulation technology of mixed signal circuit under full custom design environment. And it proposes a hierarchical simulation method for mixed circuits.5, On the basis of the relevant theoretical research of PLL, this article designs a new kind of programmable PLL named FT-X with high-performance under the SMICO. 18um CMOS technics. Simulations and emulations have shown that FT-X can work at more than 600MHz with the jitter less than 20ps. |
