A 622Mb/s 4:1 Multiplexer Design In 0.6μm CMOS Technology

A multiplexer is one of key function modules of optic-fiber systems. Because the bit rates of multiplexers are very high, many engineers of the world used GaAs, Bipolar Si and BiCMOS process to realize the high-speed multiplexers in the past decades. With the development of the CMOS process , it is possible to realize the high-speed digital ICs by CMOS process. This paper presents the design of a 0.6μm CMOS 4:1 Multiplexer . This is a discussion on high-speed digital IC design.There are three structures of multiplexer : serial, parallel and tree. Serial structure multiplexer shows small scale, easy clock, but high power consumption. Parallel multiplexer has the features of small scale, but difficult clock. Tree multiplexer has the merits of easy clock, low power consumption and multi-channel multiplexing, but its scale is large. This paper uses tree structure and Source Coupled FET Logic circuits to build the 4:1 multiplexer.The simulation was finished by SmartSpice. During the process of adjusting parameters, a new means, observing and grouping, was brought up. The simulation results demonstrated that this circuit could operate at a bit rate of 622Mb/s and its power consumption is lower than 0.4W with 5V voltage supplement.