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Low Power flip-flop Analysis and Design for use in Network Processors

Posted on:2011-03-11Degree:M.A.ScType:Thesis
University:Carleton University (Canada)Candidate:Arunachalam, SomasundaramFull Text:PDF
GTID:2448390002450543Subject:Engineering
Abstract/Summary:
This thesis explores the topic of power consumption reduction of flip- flop circuits. In order to determine the impact of the low power flip-flops on circuits, common circuits are extracted by analyzing a VLSI System. The VLSI system used for analysis in this thesis is network processors. A measurement methodology is laid out in order to standardize power and performance measurements. The common circuits, 16-bit counter, 32-bit counter, 8-bit PRBS generator, and 8-bit data bus, are simulated and total power consumption is measured.;Power consumption for four existing flip-flops technologies, standard master-slave flip-flop, clock gated flip-flop, data transition look-ahead flip-flop, and clock-on-demand flip-flop, are measured and analyzed. Three flip-flop topologies, clock on demand with shared pulse generator, clock gating on demand, and clock gated data transition look-ahead flip-flop, are introduced that combine different power saving techniques to reduce the total active power consumption of the circuits they are implemented in. The proposed flip-flops share pulse-generators between many storage elements to reduce power consumption overhead. The clock signals are gated when the data input and the data output to the storage elements do not toggle. Simulations are run in IBM 65 nm CMOS technology. Utilizing clock gated data transition look-ahead flip-flop in a 16-bit counter reduces power consumption by 90% over a counter implemented with standard master slave flip-flop when counter is not being incremented and power consumption is reduced by 25% when the counter is incremented every cycle. Utilizing clock gating on demand flip-flop for an 8-bit data bus implementation reduces power consumption by 90% over data bus implemented with standard master-slave flip-flop when activity factor is 0%. However the data-bus implemented with master slave flip-flop has 4.5% lower power consumption than the data-bus implemented with clock gating on demand flip-flop.
Keywords/Search Tags:Power, Flip-flop, Data, Clock, Circuits, Implemented, Demand
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