Research On Digital Circuits Low Power Design Method Based On Multi Bit Flip Flop

Now,the power of the integrated circuit is more than 100 watts.How to reduce the power become the primary problem of the integrated circuit design.When the chip is working,the dynamic power accounts for 90% of the total power,and the dynamic power on the clock path accounts for 40%.How to reduce the dynamic power is the key to achieve low-power design,and the design method to reduce the dynamic power on the clock path is often more simple and efficient.Now,widely used low power design includes multi threshold voltage technology,gated clock technology,multi voltage supply technology,and netlist optimization technology,but they also cannot meet the claim in low power IC design.So this paper towards the dynamic power on the clock path to design a multi bit flip flop by using the back-end design to reduce the number of the inverter on the clock path,thereby the dynamic power of the clock path is reduce,also this method helps achieve a smaller area.The main work of this paper includes four things.First,this paper introduces the composition of integrated circuit power.Based on this,the paper designs a multi bit flip flop to reduce the power on clock path.Then this paper introduces the structure of multi bit flip flop and working principle,etc.Next this paper verifies the function of the design to show the feasibility of the design.Second based on the characteristics of the multi bit flip flop,SHA256 algorithm is selected to verify the performance of this design method in practical application.Firstly,this paper briefly introduces the SHA256 algorithm and the module design.Then,expound the test flow of the module.Finally,complete the function verification of the front-end design to show the correctness of the module design.Third based on SMIC 55 nm process aiming at SHA256 algorithm module,complete the DC synthesis,layout and routing of the test process.Compare with the area,power and timing report obtained by DC synthesis through using four different flip flop design methods(single bit flip flop,two bit flip flop,four bit flip flop,mixing bit flip flop),the report shows that it can effectively reduce the area about 3% when using multi bit flip flop.And when using four bit flip flop,the slack is 0.2473.When using single bit flip flop,the slack is 0.2650.It shows that multi bit flip flop would reduce the timing,but still meet the design requirements.Fourth,use prime time and VCS tool to analyze the temporal analysis and dynamic simulation.Then verify its function,and export the VCD file for the final power analysis to get the actual power.The result shows that compared with using single bit flip flop,two bit flip flop reduces power by 12%,mixing bit flip flop reduce power by 18%,and four bit flip flop reduce power by 35%.The above results show that the use of multi bit flip flop technology can effectively reduces the clock path power,and the four bit flip flop get the best result.Also this method can reduce the chip area.