Design Of High-performace BiCMOS Flip-flops

As the speed, scale and function of integrated circuit develope rapidly, the demand for high speed and low power increase greatly. Flip-flops are the crucial sequential elements of the digital integrated circuits, which have an important impact on the performance of integrated circuits. Design of high-performance flip-flops has been paid great concern.BiCMOS circuits, which not only have low power, high integration density of CMOS circuits but also have high speed and powerful drive ability of bipolar circuits, have become one of the research focuses worldwidely. Compared with traditional master-slave flip-flops, pulse triggered flip-flops which have simpler structure; soft edge and smaller delay are in more and more use. A novel general structure and design method for dual-edge triggered flip-flops based on BiCMOS are proposed and three high-performance BiCMOS dual-edge triggered D flip-flops (PNP-PNP-DEDFF, PNP-NPN-DEDFF and NPN-NPN-DEDFF) according to the structure are presented in this paper. Meanwhile, to fulfill the needs of level converting in low-power integrated circuits with a dual-supply, a novel genenal structure and design method for BiCMOS dual-edge triggered level-converting flip-flops areproposed, according to which three kinds of BiCMOS dual-edge triggered level-converting flip-flops are designed as well (PNP-PNP-DELCFF, NPN-NPN-DELCFF and PNP-NPN-DELCFF).MCML circuits have been paid more and more attention for their high speed, low swing and their ablility of dissipating less power than conventional CMOS circuits at high frequency. The multi-valued logic can improve the information density of integrated circuits and provides an effective solution to the rapid increase of interconnect lines. Based on MCML and multi-valued design theory, a novel MCML ternary D flip-flop and a MCML quaternary D flip-flop (MCML-TDFF and MCML-QDFF) based on CMOS have been proposed. Using similar design method, finaly a novel CML ternary D flip-flop based on BiCMOS (BiCMOS-CML-TDFF) has been designed, which combines advantages of both BiCMOS and CML and is suitable for high-speed and high-frequency multi-valued circuits. All of the flip-flops proposed in this paper are simulated by HSPICE using TSMC180nm process. Simulation results show that proposed flip-flops have outstanding transient performance and correct logic function. Compared with three advanced counterparts, proposed PNP-PNP-DEDFF, PNP-NPN-DEDFF and NPN-NPN-DEDFF gains improvements of78.4%～91.2%,80.8%～92.1%and80.0%～91.8%in power consumption,48.1%～95.5%,49.1%～95.6%and45.5%～95.3%in PDP respctively. furthermore, proposed BiCMOS dual-edge triggered flip-flops can drive load of500fF well, drive ability of which are much stronger than CMOS pulse-triggered flip-flops. Compared with three existing advanced LCFFs, proposed PNP-PNP-DELCFF, NPN-NPN-DELCFF and PNP-NPN-DELCFF gains improvements of15.5%-48.5%,3.5%～41.2%and8.1%～43.9%in D-Q delay,9.2%～48.9%,3.0%～42.7%and3.7%～43.1%in PDP respectively. Furthermore, proposed BiCMOS dual-edge triggered LCFFs can drive load of100fF, drive ability of which outperforms CMOS LCFFs. Compared with three advanced ternary D flip-flops, proposed MCML-TDFF and BiCMOS-CML-TDFF gains improvements of94.8%～98.1%and95.6%～98.4in average D-Q delay,29.7%～75.1%and16.2%～70.4%in PDP respectively. The results demostrate that proposed general structure and design methods for BiCMOS pulse-triggered D flip-flops and level converting flip-flops, including BiCMOS current-mode logic flip-flops are with simple structure and low PDP. All of them are suitable in high-speed and low-power application.