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Design Of High-Speed Multiplexer

Posted on:2007-05-21Degree:MasterType:Thesis
Country:ChinaCandidate:Y LingFull Text:PDF
GTID:2178360212465420Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Optic-fiber Communication System has been the principal part of information super-highway in recent years. So it is important to design high-speed integrated circuits for optical transmission system with independent property.Multiplexer (parallel-to-serial converter) is one of the key function modules of optical transmission system. Three basic structures for multiplexer, i.e. serial, parallel and tree, are discussed. Serial-type multiplexer shows low power dissipation at low rate. Tree-type has the feature of high-speed, but large scale. So, a 16:1 MUX can be realized with the appropriate combination of the three structures to optimize in ways of rate, chip area and power assumption. Besides, different circuit design and the selection of parameters at different rates can optimize also.A 2.5Gb/s 16:1 MUX designed with TSMC 0.35μm CMOS technology is presented in this paper, constructed in the combined architecture of serial-type structure at low-speed part and tree-type at high-speed part. Simulation results show that the highest speed of the output can be 3.5Gb/s and its power dissipation is less than 300mW with 3.3V power supply. This paper also describes a 10Gb/s 16:1 MUX using TSMC 0.18μm CMOS process. The MUX is constructed in tree-type structure. A dual-phase dynamic-pseudo NMOS logic is proposed for low-speed multiplexer while SCFL logic for high-speed multiplexer. The measurement of the MUX shows that the chip can work at 10Gb/s and its power dissipation is 210mW with 1.8V power supply.
Keywords/Search Tags:SDH(Synchronous Digital Hierarchy), MUX (Multiplexer), CMOS, dual-phase dynamic-pseudo NMOS logic, SCFL(Source Coupled FET Logic), high-speed digital Integrated Circuits
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