High-Speed And Low-Power Ternary Logic Circuits Design Based On MCML/TG

Recently, VLSI technology has considered chip area, operation speed and power consumption. The traditional CMOS logic circuits dissipate the power only when the load is charging and discharging. Therefore, the power consumption of the CMOS logic circuits is generally small at low frequency. However, by the increasing frequency reaching to 1 GHz, the power consumption of traditional CMOS circuits increase rapidly and the advantage on power consumption will be reduced. In addition, the considerable internal noise of the traditional CMOS circuits hinders the SOC integration of sensitive analog and digital circuits. However, MCML can simultaneously satisfy the requirements of power consumption and speed, and provide a friendly mixed environment.Currently at home and abroad, the researches of MCML circuits mainly focuses on two-valued circuits, such as the analysis of the characteristics of the circuits, circuits designing and improvement of time delay and power consumption, etc. The paper is mainly concentrated on the ternary MCML circuits. Firstly, by analyzing the characteristic of MCML and TG circuits, this paper proposes an idea of designing circuits based on combining the two structures. This mixed structure MCML/TG is mainly composed of MCML and TG, the control signal is produced by MCML and TG is responsible for transmission. Secondly, circuits designing based on the MCML/TG structure in the Post algebraic system and Mode algebraic system is proposed; then using the designed 3-T operator, the paper proposes one kind of full adder. Thirdly, designing of D-latch circuit based on the structure of MCML/TG is proposed and master-slave flip-flop is realized based on the latch; then the paper proposes the double-edge-triggered flip-flop based on ternary clock and discusses the designing of ternary JKL flip-flop analytically. Finally, this paper simulates the designed circuits by Hspice, and using the idea of multi-valued logic designing to conduct the switch-level designing of two-valued MCML/TG circuits. The proposed logic is validated by simulations of Hspice based on the TSMC 0.18 um MOS technology with 1.8v power supply voltage. The simulation results show the power dissipation of the MCML/TG circuits is almost independent of clock frequency, the input and output voltage is consistent, and the propagation delay is improved greatly compared to the conventional CMOS circuits. Moreover, the structure is symmetrical and simple.