Design Of High-Speed 4:1 Multiplexer In 0.6μm CMOS Technology

With the development of telecommunication networks, computer networks and Internet, it is urgent to build information highway. Optic-fiber communication systems are the principal and important parts of modern communication for its merits such as great capacity, long transmit distance, economizing energy source, anti interference and anti radiation etc. The bandwidth and speed of the current fibers is very large while a single way of digital signals is relatively low. One of the most important technologies to increase the speed is to combine multiple narrow band or low rate signal channels into a high rate one. So, Multiplexer (parallel-to-serial converter) is one of the key function modules of optical.Three basic structures for multiplexer, i.e. serial, parallel and tree, are discussed. Serial-type multiplexer shows low power dissipation at low rate. Parallel multiplexer has the features of small scale, but difficult clock. Tree-type has the feature of high-speed, but large scale. Besides, different circuit design and the selection of parameters at different rates can optimize also.System integration, lower cost and lower power requirements in optic-fiber transmission system have made the TSMC 0.6μm CMOS the technology of choices for high-speed multiplexing. This paper uses improved tree structure decreases the speed of most modules, which makes design easier, and decrease the power consumption. The system includes a high speed 1:2 MUX cell, two low speed 1:2 MUX cells, 1:2 divider, input and output buffers for data and clock. Low speed 1:2 MUX cells is constructed in CMOS logic circuit because its circuit structure is simple and power assumption is low, high speed 1:2 MUX cells is constructed in source couple FET logic circuit because its interference rejection is strong and speed is high. Then, improved parallelism-type structure was used in high speed 2:1 MUX cells for obtain relaxed timing condition and eliminate clock skew. The difference between the phases enter the 2-bit selector is adjusted by latch in data channels and buffer in clock channels in these units. The half-rate architecture is adopted to reduce the complexity of clock design and save power.The simulation results demonstrated that this circuit could operate at a bit rate of 622Mb/s, quality of eye diagram is very good, power assumption is lower than 0.2W with 5V voltage supplement.