Fiber Multiplexer Cmos Integrated Circuit Design

Nearly, the communication in our country is developing much further. In 2004 the budget of optic fiber communication of our country will reach 5.5 billion dollars. But the main chip using in the optical-fiber-communication is mostly depending on importation. It is far away from the aim that we want to be the communication country. So it is much important to have our own integrate circuit which is using in optical-fiber-transmission system. It has great meaning for the information highway building of our country.Multiplexer (parallel-to-serial converter) is one of the key function modules of optical-transmission-system, there are three structures of multiplexer: serial, parallel and tree. Each has its own characteristics, this paper uses tree structure to build the 4:1 multiplexer with SCFL circuit, which makes design easier, and reduces the chip area, and decreases the power consumption.Under the rules of Synchronous Digital Hierarchy, the bit rates of Multiplexers are all upper Gb/s at present, in the past, many engineers of the world used GaAs, Bipolar Si and BiCMOS processes to realize the high-speed Multiplexers. This paper presents the design of a 0.18um CMOS 4:1 Multiplexer used in SDH-64.The measurement of the Mux chip shows that this chip can operate at 10Gb/s, and its power consumption is less than 400mW with 1.8V voltage supplement. and it amplifies the input differential signal amplitude from 300mV to small less than 200mV.