Design Of Low Power CMOS Circuits Based On Multi-threshold Technique

Low power design has been becoming an important part in the design of digital systems because the power dissipation of current digital systems increases rapidly. As the process enters deep submicron stage, the static power dissipation of CMOS circuits takes a bigger part in its total power dissipation and rises exponentially with the feature size decrease. Thus, the static power dissipation does not approach to null anymore and can't be paid little attention again.First, this paper expatiates an simple but effective way to reduce the static power dissipation of CMOS circuits -the principle of multi-threshold CMOS circuits, analyses the influences of multi-threshold technology to CMOS circuits and summarizes them. The paper presented that the sleep signal for controlling high Vt NMOS can be replaced by redundancy checking signal. Second, it designs all kinds of multi-threshold logic cells: multi-threshold inverter, multi-threshold Nand-gate and multi-threshold Nor-gate. According to the idea of multi-threshold, a new kind of multi-threshold priority encoder is designed. This kind of encoder can restrain not only the leakage current but also redundancy of CMOS circuits, thus it reduces the static power dissipation as well as the dynamic power dissipation. Third, the idea of multi-threshold is applied to flip-flop, as a result, two new kinds of flip-flops are designed, which are directly pre-settable master-slave multi-threshold flip-flop and clock-competitive multi-threshold flip-flop. Compared to traditional ones, these, multi-threshold flip-flops have simpler structures and consume obviously less power. Especially, the clock-racing multi-threshold flip-flop can decreases the leakage power and the power dissipation of clock network.