Design And Implementation Of Clock Generation Circuit Based On 10/100M Ethernet PHY Chip

Since the beginning of the 20 th century,human society has entered a new era of information with the combination of computers,networks,and communication technologies.Thanks to the development of the information technology,network technology has also developed rapidly.Ethernet is currently the most commonly used LAN technology.In recent years,Ethernet technology has also developed rapidly.As an important part of the Ethernet network,the Ethernet PHY(physical layer)chip always supports the high-speed development of Ethernet.As a key module in the Ethernet PHY chip,the clock generation circuit largely determines the performance of the Ethernet.Based on the purpose of studying the IEEE 802.3 protocol,this thesis uses a standard CMOS process to implement a clock generation circuit for a 10/100 Mbps Ethernet PHY chip.The clock generation circuit originally designed is mainly composed of voltage and current reference circuits,low-dropout linear voltage regulators,two charge pump phase-locked loops(CPPLL),and Current Mode Logic(CML)circuit.The thesis first introduces the Ethernet transceiver structure and derives the main components of the clock generation circuit.Second,it analyzes each circuit module theoretically,deduces the parameters of each circuit,and completes the module simulation verification.Finally,it is based on the standard CMOS process,Completed the layout design of the clock generation circuit in 10M/100 Mbps Ethernet.The main technical indicators of this design are: in typical conditions,the typical jitter of phase-locked loop is less than 10 ps at 125 MHz.In the operating temperature range of-55°C to 125°C,the temperature coefficient of the voltage reference is less than 50ppm/?.The LDO output voltage is 1.8V±5% and output current is typically 60 m A.The LDO also has a overcurrent protection of 120 m A.After the layout,the post-simulation results show that the jitter of the output signal is typically only 6.5ps at 125MHz;in the operating temperature range of-55°C to 125°C.The temperature coefficient of the voltage reference is a maximum of 47 ppm/°C.The output voltage of LDO is 1.795 V,with 107 m A overcurrent protection.The performance of the circuit is excellent in various PVT combinations.The expected design result of the entire chip is riched.