SerDes Interface Circuit Design Of Gigabit Ethernet

With the continuous improvement of network communication technology and integrated circuit manufacturing technology,the exchange of information between systems has become larger.When traditional parallel transmission interface technology transmits data,it has shortcomings such as weak anti-interference ability,large clock skew and short transmission distance,which causes the transmission interface to become a bottleneck that limits the data transmission rate.In order to meet the increasing demand for bandwidth,the high-speed serial interface SerDes has gradually replaced the traditional parallel interface and has become the mainstream technology of the high-speed interface.SerDes usually adopts a differential transmission method,which has the advantages of strong anti-interference ability and long transmission distance.SerDes as a mainstream serial transmission technology is widely used in the physical layer of the high-speed serial communication field.The SerDes interface circuit designed in this article is used in a Gigabit Ethernet physical layer network card chip to complete data transmission and reception in the GMII to1000BASE-X mode.Through the research of the SerDes system structure,the SerDes circuit is designed based on 0.13?m CMOS process.First of all,this article studies the overall architecture of the SerDes sender,and designs and simulates the key modules of the entire sender,such as 8B/10B encoding module,parallel-to-serial conversion module,etc.In order to solve the problem of baseline drift and unbalanced code stream in the process of data transmission in the fiber channel,the physical coding layer adopts 8B/10B coding.Through the research and analysis of 8B/10B coding rules and internal correlation,combined with table look-up method and logic expression method,the 8B/10B coding circuit is designed.This coding circuit simplifies the 8B/10B code table and improves the coding speed.The parallel-to-serial conversion circuit is designed with a hybrid structure of multi-phase clock type and tree type,which realizes the parallel-to-serial conversion of 10b parallel data.The designed coding circuit and parallel-serial conversion circuit are simulated by simulation tools,and the simulation results show that the designed circuit functions normally.Secondly,this article studies the overall architecture of the SerDes receiver,and designs and simulates the key modules of the receiver,such as clock data recovery module,serial-to-parallel conversion module and 8B/10B decoding module.Based on the traditional dual-loop CDR structure,a data clock recovery circuit based on the 1/4 rate of the phase interpolator is designed.Compared with the traditional structure,the recovered clock and data have low jitter and the circuit has a fast response speed.The peak-to-peak jitter of the clock and data recovered by the CDR circuit are 0.013 UI and 0.016 UI,respectively.Based on the working principle of 1/4 rate phase detection,the serial-parallel conversion circuit is used to perform serial-to-parallel conversion on the recovered four-channel data signals to complete the conversion of high-speed serial data to parallel data.The parallel 10b data is decoded by8B/10B decoder.In this paper,the decoding circuit and polarity error detection circuit are optimized by introducing intermediate variables,and a combinational logic method is used to design an 8B/10B decoding circuit with error checking function.Compared with the classic IBM decoder,the design of the 8B/10B decoder reduces the number of logic layers,improves the decoding speed and reduces the chip area.And use simulation tools to simulate and verify the designed clock data recovery circuit,serial-to-parallel conversion circuit and 8B/10B decoding circuit.The simulation results show that the designed circuit functions are correct.Finally,after the SerDes circuit design is completed,complete the layout design of the SerDes and perform board-level testing of the taped-out chip.The SerDes layout area is654×477?m~2.The chip is tested at the board level through the test platform.The test results show that the SerDes circuit integrated in the Gigabit Ethernet physical layer network card chip has normal data transmission and reception functions,and the data transmission rate can reach 1.25 Gbps,in full duplex mode,the total power consumption is 97.5 m W.Using an oscilloscope to test the eye diagrams of the sender and receiver data,the total jitter TJ of the sender and receiver data is 142.6 ps and 225.7 ps,respectively.