Design And Application Of Generic FIFO

Designers must solve the problem that is how to match different data transferring speed in different systems and avoid to cover existing data, lose transferring data and read invalid data. Fortunately, the FIFO memory can be employed to deal with the data transferring problem well.In the thesis, The generic FIFO memory will be classified as the single clock, the dual-clock and the LFSR generic FIFO memory in order to analyze and design the FIFO .Finally, by designing four FIFOs to cooperate in harmony,the job of buffering and storing data that is transmitted from interfaces of the ASIC chip of image processing based on Multilevel Filter is finished, the speed of data processing and transmitting is improved. There are two methods to be used to design the single clock generic FIFO memory. In the single clock FIFO memory design, the combinatorial and registered status outputs are designed as two output ways so that users choose one way to output status considering design requirements. Similarly, the paper employs two methods to realize the dual-clock FIFO memory. Some challenges exist in the design of the dual-clock FIFO memory, the metastable disturbance has been settled well by designing the Gray-code dual-clock generic FIFO memory. Because LFSRs inherently remember their previous value, the design of the LFSR generic FIFO memory takes advantage of much less logic cells to complete addressing read and write addresses at a faster speed. In the design of the ASIC chip of image processing based on Multilevel Filter, the FIFOs are designed to transferring data successfully.The author simulates and synthesizes every design part in the thesis, analyzes the results of simulation and synthesis and testifies that the study is successful.