Studying Of Design-for-Test For Embedded IP Cores

With the development of VDSM technology and IP-Reuse based SoC Design, the traditional IC industries begin to reform. IP-based SoC design separates system integration from function modular design, thus reducing the difficulty and scale of former design, and the designer can really bring themselves into play. And such situation is also a good chance for Chinese microelectronics industries which are always trying hard to catch up with the world-class technology.The scale of the IC continuously enlarges, and reusing embedded IP cores in SoC design become the trend. But the source of the cores differs, the design has little compatiblility and the chip circuits become much more complex, the final test of SoC becomes a real big problem. The cost of test dramatically increases to be 78%~80% of the whole cost of product, and increase the time to market. So, considering and implementing a test early in the stage of the whole design process becomes an important task."Basic Research of Semiconductor Integrated System on a Chip" is a major program that is funded by National Nature Science Foundation of China. It's goal is to catch up with the world trend and do some basic and profound research of most-needed-to-solve problems in SoC design to provide scientific method for micro-technology and IC industries. Design-for-Test for SoC is the main project.Considering the above reasons, the author consults a wide range of documents about DFT design in SoC, does a good research theoretically and practically. Nowadays, FPGA has the great potential in IP reuse based SoC design. The author considers the hot technology and also does a great research of it. Hopefully, with the author's great effort in research of DFT for SoCs, more IC designers will occur and willing to devote themselves to our country's basic research of IC design field.