Study On ATE Based Verification And Testing Techniques Of FPGA Devices

Field programmable gate array (FPGA) is reprogrammable and able to modify and rewrite the circuit system according to the need of users. This enables the FPGA to have a wide application scope without special customization. Thus, FPGA is favored by more and more industries and people, which leads to its rapid development. With the penetration of the FPGA and the improvement of the manufacturing technology, higher requirements are brought out on FPGA security and reliability. A lot of experts and researchers are dedicated themselves to the FPGA test methods and technologies. ATE-based FPGA test technology has advantages of high test efficiency, portability, fault coverage and versatility, and it also has practical application meaning. In this thesis, Teradyne UltraFLEX devices are used as a platform, and FPGA chips of the Spartan-3 series from the Xilinx are used as study objects. The divide-and-conquer method, one-dimensional array method, exhaustive method and memory test method are employed to investigate the programmable resource test of the FPGA.The major contents of this thesis are as follows:The first is the design of the test circuit board. The signals of the FPGA will be attenuated when encountering impedance mismatch. This mismatch will cause subversive test results since the sensibility of the ATE test. Therefore, we adopt the Altium Design DXP to conduct placement and routing and draw the circuit board for the selected FPGA chip. The impedance of the routing will be well controlled. The circuit board is printed by manufacturers and welded by ourselves. Finally, we test the welded circuit board to exclude faults of bridge connection and open circuit among elements in the board.The second is the development of the ATE program, debugging and FPGA testing. For the effective test of the FPGA, we develop test programs for different logic modules of the FPGA in the IG-XL software platform of the Teradyne UltraFLEX. We also experiment on the test programs in a simulation platform to optimize the test code. This reduces the time of FPGA test configuration, improves the test speed and in turn reduces the test cost of the FPGA chip.Finally, we conclude the researches in the thesis and plan the future works.