Design And Implementation Of Test System For SPI Interface Memory Chip

Chip testing plays an important part in IC manufacture.An excellent test project can greatly shorten the time from design to product.With the development of society,a new material of magnetic random access memory has become one of the hot research directions.Considering the characteristics of previous generation products,it also has advantages in density and access rate.It has a good development space in the fields of artificial intelligence,automotive electronics,intelligent wear and so on.The progress of So C technology makes people's life more amusing.All kinds of intelligent electronic devices can be seen everyplace.The normal operation of these electronic devices is inseparable from the memory.On the one hand,memory can be used to save system programs;on the other hand,it can store real-time data.Therefore,with the progress of So C technique,the memory field is facing new dare.Memory testing is existed in all aspects of IC design and production.With the continuous advance of semiconductor technology,there are more and more trouble in the process of memory manufacturing.At this time,we need to design a test system to adapt to various situations.Magnetic random access memory(MRAM)is tested in this paper,the main detail are as show below :1.First discuss the current important position of integrated circuits in our country,and the resistance of Western countries has increased in recent years.Then it introduces several main methods in the field of chip testing at home and abroad,including built-in self-test,probe card test,ATE and FPGA test.The realizable of designing FPGA test system is analyzed.2.This paper assorts memories and introduces the feature of volatile memory and non-volatile memory.Starting from the nonvolatile memory,the working theory and inside fabric of the memory under test are introduced.According to the structure of memory,the fault model of memory is studied,including address decoding fault,memory array fault and read-write logic fault.The test algorithm based on fault model is introduced.3.The hardware composition of the test system is introduced.From the beginning of the test process,the overall framework of the test system is introduced.According to the framework,the peripheral circuit and FPGA minimum system used in the system design are introduced.4.FPGA development,combined with the timing of each module to design the driver.Finally,the code is downloaded to FPGA to complete the construction of the test platform,and the debugging of the test platform is completed according to the timing of 4Mbit magnetic random access memory of 40 nm process to be tested;The test results show that the system can achieve six kinds of function test,and meet the needs of the chip under test.The test system designed this time has two characteristics: One is to make the system more flexible by using the Micro Blaze soft core.The second is to use the Socket board to fix the chip under test.Different types of chips can be equipped with the corresponding Socket board.During the test,the core board does not need to be replaced,only the Socket board can be replaced;this is beneficial to increase the scalability of the test system.